– Up to Four Banks of General-Purpose I/O（GPIO） Pins

– 32 GPIO Pins per Bank （Multiplexed WithOther Functional Pins）

– GPIO Pins Can be Used as Interrupt Inputs（up to Two Interrupt Inputs per Bank）

– Up to Three External DMA Event Inputs that canAlso be Used as Interrupt Inputs

– Eight 32-Bit General-Purpose Timers

– DMTIMER1 is a 1-ms Timer Used forOperating System （OS） Ticks

– DMTIMER4–DMTIMER7 are Pinned Out

– One Watchdog Timer

– SGX530 3D Graphics Engine

– Tile-Based Architecture Delivering up to 20Million Polygons per Second

– Universal Scalable Shader Engine （USSE） isa Multithreaded Engine Incorporating Pixel

and Vertex Shader Functionality

– Advanced Shader Feature Set in Excess ofMicrosoft VS3.0， PS3.0， and OGL2.0

– Industry Standard API Support of Direct3DMobile， OGL-ES 1.1 and 2.0， and OpenMax

– Fine-Grained Task Switching， LoadBalancing， and Power Management

– Advanced Geometry DMA-Driven Operationfor Minimum CPU Interaction

– Programmable High-Quality Image Anti-Aliasing

– Fully Virtualized Memory Addressing for OSOperation in a Unified Memory Architecture

– LCD Controller

– Up to 24-Bit Data Output; 8 Bits per Pixel（RGB）

– Resolution up to 2048 × 2048 （WithMaximum 126-MHz Pixel Clock）

– Integrated LCD Interface Display Driver（LIDD） Controller

– Integrated Raster Controller

– Integrated DMA Engine to Pull Data from theExternal Frame Buffer Without Burdening theProcessor via Interrupts or a Firmware Timer

– 512-Word Deep Internal FIFO

– Supported Display Types：

– Character Displays - Uses LIDD Controllerto Program these Displays

– Passive Matrix LCD Displays - Uses LCDRaster Display Controller to ProvideTiming and Data for Constant GraphicsRefresh to a Passive Display

– Active Matrix LCD Displays – UsesExternal Frame Buffer Space and theInternal DMA Engine to Drive StreamingData to the Panel

– 12-Bit Successive Approximation Register（SAR） (责任编辑：admin)