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AMIC110多协议可编工业通信处理器开发方案(2)

时间:2024-09-04 12:53来源:[db:来源] 作者:admin 点击:
– 176KB of On-Chip Boot ROM – 64KB of Dedicated RAM – Emulation and Debug - JTAG – Interrupt Controller (up to 128 InterruptRequests) • On-Chip Memory (Shared L3 RAM) – 64KB of Gen

– 176KB of On-Chip Boot ROM

– 64KB of Dedicated RAM

– Emulation and Debug - JTAG

– Interrupt Controller (up to 128 InterruptRequests)

• On-Chip Memory (Shared L3 RAM)

– 64KB of General-Purpose On-Chip MemoryController (OCMC) RAM

– Accessible to All Masters

– Supports Retention for Fast Wakeup

• External Memory Interfaces (EMIF)

– mDDR(LPDDR), DDR2, DDR3, DDR3LController:

– mDDR: 200-MHz Clock (400-MHz Data Rate)

– DDR2: 266-MHz Clock (532-MHz Data Rate)

– DDR3: 400-MHz Clock (800-MHz Data Rate)

– DDR3L: 400-MHz Clock (800-MHz DataRate)

– 16-Bit Data Bus

– 1GB of Total Addressable Space

– Supports One x16 or Two x8 Memory DeviceConfigurations

– General-Purpose Memory Controller (GPMC)

– Flexible 8-Bit and 16-Bit AsynchronousMemory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)

– Uses BCH Code to Support 4-, 8-, or 16-BitECC

– Uses Hamming Code to Support 1-Bit ECC

– Error Locator Module (ELM)

– Used in Conjunction With the GPMC toLocate Addresses of Data Errors fromSyndrome Polynomials Generated Using aBCH Algorithm

– Supports 4-, 8-, and 16-Bit per 512-ByteBlock Error Location Based on BCHAlgorithms

• Programmable Real-Time Unit Subsystem andIndustrial Communication Subsystem (PRU-ICSS)

– Supports Protocols such as EtherCAT®,PROFIBUS, PROFINET, EtherNet/IP™, and

More

– Two Programmable Real-Time Units (PRUs)

– 32-Bit Load/Store RISC Processor Capableof Running at 200 MHz

– 8KB of Instruction RAM With Single-ErrorDetection (Parity)

– 8KB of Data RAM With Single-Error Detection(Parity)

– Single-Cycle 32-Bit Multiplier With 64-BitAccumulator

– Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal (责任编辑:admin)

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